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e preliminary december 1998 order number: 290620-005 n low-cost linear flash card ? 5 volt intel ? strataflash tm memory flash technology n fast read performance ? 150 ns max access time n high-performance writes ? 12 m s typical byte write n 32 byte write buffer ? frees cpu to perform other tasks n low deep power-down current ? 145 m a maximum for 4-mb card n x16 data interface n single supply operation ? 5 v read/write n automated write and erase algorithms ? cfi and scs compliant n enhanced automated suspend options ? block erase suspend to write ? block erase suspend to read n enhanced data protection features ? flexible block locking n 100,000 erase cycles per block n 128-kbyte erase blocks the intel ? series 200 miniature cards deliver the benefits of intel ? strataflash? memory to users of portable electronic systems. capitalizing on two-bit-per-cell technology, intel strataflash memory products provide 2x the bits in 1x the space. intel strataflash memory devices are the first to bring reliable, two-bit-per-cell storage technology to the flash memory market. intel strataflash memory benefits include: more density in less space, lowest cost-per-bit nor devices, support for code and data storage, and easy migration to future devices. using the same nor-based etox? technology as intels one-bit-per-cell products, intel strataflash memory devices take advantage of 400 million units of manufacturing experience since 1988. as a result, intel strataflash components are ideal for code or data applications where high density and low cost are required. examples include networking, telecommunications, audio recording, and digital imaging. intel strataflash memory components provide a new generation of forward-compatible software support built upon the intel ? flashfile? memory architecture. by using the common flash interface (cfi) and the scaleable command set (scs), customers can take advantage of density upgrades and optimized write capabilities of future intel strataflash memory devices. manufactured on the intel ? 0.4 micron etox v process technology, intel strataflash memory provides the highest levels of quality and reliability. the 5 volt series 200 miniature cards, based on the miniature card implementers forum (mcif), employ 5 volt intel strataflash components to provide the ultimate in convenient, low-cost data storage for users of portable electronics systems. to meet the demanding requirements of diverse portable electronic system, these miniature cards are designed as small form factor removable media and are favored for their cost- effectiveness and reliability. ideal platforms for the 5 volt series 200 include digital still cameras, audio recorders, smart cellular phones and hand-held pcs. such applications require low-cost, consumer-friendly data storage media, as well as a convenient method to transport data to a pc for file manipulation and enhancement. host-based filing system software, such as flash translation layer (ftl), eliminates the need for expensive card-based microcontrollers and asics. the 5 volt series 200 flash memory miniature cards enable the consumer to enjoy compatibility across a wide range of systems, allowing easy data exc hange with ms-dos* and windows* 95-based pcs. note: this document formerly known as series 200 flash memory miniature card 4, 8, 16 mbytes . 5 volt series 200 flash memory miniature card IFM004G, ifm008g and ifm016g
information in this document is provided in connection with intel products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantabili ty, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. the IFM004G, ifm008g and ifm016g may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature, may be obtained from: intel corporation p.o. box 5937 denver, co 80217-9808 or call 1-800-879-4725 or visit intels website at http://www.intel.com copyright ? intel corporation 1998 cg-041493 * third-part y brands and names are the propert y of their respective owners
e IFM004G/ifm008g/ifm016g 3 preliminary contents page page 1.0 scope of document.................................5 2.0 product overview ...................................5 3.0 card architecture .................................6 3.1 card signal description................................7 4.0 memory control logic ........................10 4.1 bus operations ..........................................10 4.1.1 read array ..........................................10 4.1.2 output disable.....................................10 4.1.3 standby ...............................................11 4.1.4 reset/power-down..............................11 4.1.5 read identifier codes..........................12 4.1.6 write....................................................12 4.2 decode logic .............................................12 5.0 command definition...............................13 5.1 basic command set ..................................13 5.1.1 read array command.........................13 5.1.2 read identifier codes command.........15 5.1.3 read status register command .........15 5.1.4 clear status register command .........15 5.1.5 block erase command........................17 5.1.6 block erase suspend command .........17 5.1.7 word-write command.........................18 5.1.8 set block lock-bit command ..............18 5.1.9 clear block lock-bits command .........18 5.2 scaleable command set............................18 5.2.1 block write command.........................20 5.2.2 configuration command......................20 5.2.3 read query command........................20 6.0 card attribute information..............21 6.1 card information structure .........................21 6.2 attribute information structure....................21 6.3 cis data ....................................................22 7.0 electrical specifications..................26 7.1 absolute maximum ratings........................26 7.2 operating conditions..................................26 7.3 capacitance ...............................................26 7.4 dc characteristics .....................................27 7.5 ac characteristics......................................28 7.5.1 read operations..................................29 7.5.2 write operations..................................30 7.5.3 power-up timing.................................31 7.6 block erase, write, and lock-bit configuration performance........................33 8.0 packaging .................................................34 9.0 ordering information..........................35 10.0 additional information .....................35
IFM004G/ifm008g/ifm016g e 4 preliminary revision history date of revision version description 12/01/97 -001 original version 03/16/98 -002 updated front cover sheet highlights: write speed changed to 7 m s, erase cycles per block changed to 100,000 in table 5, card signal values for the card's bus operations and modes , changed conditions for word read, word write and standby operations in first sentence of paragraph 4.1.3, standby , re-defined standby mode entry conditions in table 11, cis memory map , removed cistpl_device_oc row entry, bumped-up the address locations for the final 2 row entries of the table in paragraph 6.3, cis data, eliminated all references to 4 mbC200 ns, 8 mbC 150 ns and 16 mbC150 ns card density-speed combinations and changed description entry for addresses 05h C 0dh from null to cistpl_null (in bold font) in the last row (for i cces ) of the dc characteristics table of paragraph 7.4 changed ce 1 # to cel# and ce 2 # to ceh# in note 1 of paragraph 7.5.2, write operations , restated the ce# deasserted conditions to be both ce#s (cel# and ceh#) instead of either one of the ces (cel# or ceh#) in paragraph 7.6, block erase, write, and lock-bit configuration performance , changed the typ entries for first 3 parameters (pertaining to write time) to increase write times by 16.67%; added note 6 to describe expected write time performance relative to the specified maximum and typical values, and to suggest use of busy# to maximize system performance. 05/01/98 -003 updated front cover sheet highlights: changed write speed to 6.3 m s 06/05/98 -004 updated front cover sheet highlights: changed write speed to 12 m s in paragraph 7.6 block erase, write, and lock-bit configuration performance, changed typical values for the following parameters: write buffer word write time, word write time (using word write command), and block write time (using write to buffer command) 12/21/98 -005 all densities of the 5 volt series 200 miniature card are now based on the 28f320j5. specifications were changed accordingly. name of document changed from series 200 flash memory miniature card 4, 8, 16, mbyte.
e IFM004G/ifm008g/ifm016g 5 preliminary 1.0 scope of document this datasheet describes a 5 volt intel ? strataflash? memory card architecture, ac and dc characteristics and command definitions. refer to intel order number 290606 when ordering the datasheet. 2.0 product overview the 4-, 8- and 16-mbyte flash memory cards each contain a flash memory array made up of 5 volt intel strataflash memory components. the 4- mbyte card consists of a single 4-mbyte component (product number 28f320j5) configured for x 16 operation. similarly, the 8-mbyte card consists of two 4-mbyte components (intel ? 28f320j5) configured for x16 operation. the 16-mbyte card consists of four 4-mbyte components which are configured for x16 operation. intel strataflash memory can store more than one bit per flash memory cell, reducing the size and cost of large flash memory arrays. figure 1 provides a generic block diagram which illustrates the cards functional layout and user interface. a command user interface (cui) serves as the interface between the system processor and internal operation of the cards memory device(s). a valid command sequence written to the cui initiates device automation. an internal write state machine (wsm) automatically executes the algorithms and timings necessary for block erase, write, and lock-bit configuration operations. each intel strataflash memory device incorporates a 16 word (32 byte) write buffer. this dramatically improves write performance by optimizing a flash memory devices programming algorithm, thereby freeing the cpu from writing data and polling status on a word-by-word basis. the 32-byte buffer can be loaded at full bus speed; then a single command can be issued to transfer the buffer into the flash memory array. while the write state machine (wsm) is handling all of the flash memory programming details for a memory write operation, the host cpu is free to perform other tasks. the 4-, 8-, and 16-mbyte cards contain, respectively, 32, 64, and 128 separate 128-kbyte erase blocks. a block erase operation erases one of the 128-kbyte blo cks typically within one secondindependent of other blo cks. each block can be independently erased 100,000 times. block erase suspend mode allows system software to suspend block erase to read data from or write data to any other block.
IFM004G/ifm008g/ifm016g e 6 preliminary decoder busy# cel# ceh# a 22 28f320j5 sts ce 2 ce 1 ce 0 28f320j5 sts ce 2 ce 1 ce 0 2 d[15:0] oe# we# reset# a[21:0] d[15:0] a 0 oe# we# rp# a[22:1] d[15:0] a 0 oe# we# rp# a[22:1] and 0620_01 figure 1. 8-mbyte flash memory card block diagram showing major functional elements 3.0 card architecture the 5 volt series 200 miniature card implements the functionality of the miniature card specification with x16 (word-wide) data transfers. the card does not support individual 8-bit (byte) wide memory data transfers as the cards memory devices(s) and data bus interface are structured word-wide. the card ignores the miniature card interface signal bs#8 (for selecting between byte and word host data transfers) and assumes the bs#8 signal to be high (for word access between the host and card). various information about the card is contained in an attribute information structure (ais) as defined in the pcmcia miniature card specification. the ais is stored in block 0 of the cards memory array. the high byte of the ais is always ffh, the low byte contains the actual ais data.
e IFM004G/ifm008g/ifm016g 7 preliminary 3.1 card signal description the signals for the 5 volt series 200 miniature card are listed in table 1 and table 2. they comply with the miniature card specification. table 3 and table 4 describes the signals. table 1. 5 volt series 200 flash memory miniature card interface signals pad # signal name pad # signal name pad # signal name 1a 18 21 d 12 41 a 4 2a 16 22 d 10 42 cel# 3a 14 23 d 9 43 a 1 4v ccr (1) 24 d 0 44 casl# (1) 5 ceh# 25 d 2 45 cash# (1) 6a 11 26 d 4 46 cd# 7a 9 27 rfu 47 a 21 (4) 8a 8 28 d 7 48 busy# 9a 6 29 sda (1) 49 we# 10 a 5 30 scl (1) 50 d 14 11 a 3 31 a 19 51 rfu (1,2) 12 a 2 32 a 17 52 d 11 13 a 0 33 a 15 53 vs2# (1) 14 ras# (1) 34 a 13 54 d 8 15 a 24 (1) 35 a 12 55 d 1 16 a 23 (1) 36 reset# 56 d 3 17 a 22 (1) 37 a 10 57 d 5 18 oe# 38 vs1# 58 d 6 19 d 15 39 a 7 59 rfu (1,2) 20 d 13 40 bs8# (1) 60 a 20 (3) notes: 1. these signals make no internal connection into the card. 2. reserved pins must not be driven by the host. they should be left floating. 3. a 21 and a 22 are not decoded on the 4-mbyte card. 4. a 22 is not decoded on the 8-mbyte card.
IFM004G/ifm008g/ifm016g e 8 preliminary table 2. 5 volt series 200 flash memory miniature card power/insertion signals signal # signal name 61 gnd 62 cins# 63 v cc table 3. 5 volt series 200 flash memory miniature card interface signal description symbol type name and function a 0 Ca 24 input address inputs: addresses a 0 through a 24 enable direct addressing of up to 64 mb of memory on the card. the memory will wrap at the card density boundary. the system should not try to access memory beyond the cards density, since the upper addresses are not decoded. d 0 Cd 15 input/ output data input/output: d 0 through d 15 constitute the bi-directional data bus. d 15 is the most significant bit. cel#, ceh# input card enable low & high: cel# enables accesses on the low byte of the data bus d 0 C7 . ceh# enables accesses on the high byte of the data bus d 8C15 . both cel# and ceh# are active low signals. a host is expected to assert both cel# and ceh# as the cards memory provides for word-wide data transfers but not byte-wide data transfers. oe# input output enable: active low signal, enables read data from the memory card. we# input write enable: active low signal, enables write data to the memory card. busy# output busy: active low signal, indicates the status of internally timed erase or write activities. a high output indicates the memory card is ready to accept another command. cd# output card detect: active low signal, provides for card insertion detection. cd# connects to ground internally on the memory card, and will be forced low when the cd# interface signal connects to the host. reset# input reset: active low input signal, resets the devices command user interface and places the card into a deep power-down mode. the host must drive this signal. bs8# input 8-bit bus width: this signal is not connected on the 5 volt series 200 miniature card. the card assumes the miniature card implementers forum specifications high state definition of this signal to provide for only 16-bit data transfers between the host and card. vs1#, vs2# output voltage sense: notifies the host socket of the cards v cc requirements. vs 1 and vs 2 are both left open to indicate that the card only operates at 5 v. rfu ? reserved for future use
e IFM004G/ifm008g/ifm016g 9 preliminary table 4. 5 volt series 200 flash memory miniature card power/insertion signal description symbol type name and function cins# output card insertion detect: this signal provides for early card insertion detection. cins# connects to ground internally on the memory card, and will be forced low when the power/insertion signals connect to the host. v cc - card power supply: 5 v gnd - ground 60 59 30 29 vcc (63) cins# (62) gnd (61) 1 2 31 32 miniature card bottomside 0620_02p figure 2. card interface signal assignment
IFM004G/ifm008g/ifm016g e 10 preliminary 4.0 memory control logic 4.1 bus operations the host executes memory read, write and erase operations by issuing the appropriate command to the flash memorys command user interface (cui). the cui, which supports the command set of the cards memory devices, serves as the interface between the host processor and internal operation of a flash device. commands can be issued to the cui using standard microprocessor bus cycles. table 5 lists the miniature cards bus operations and modes. for each listed bus operation or mode the table defines the value of the cards relevant bus and control signals. 4.1.1 read array the host enables reads from the card by writing the appropriate read command to the cui. the memory devices automatically reset to read array mode upon initial card power-up or after card reset. cel#, ceh#, and oe# must be logically active to obtain 16 data bits at the outputs. the card enable (cel# and ceh#) inputs together with the cards address inputs are used to select the addressed devices. output enable (oe#) is the data input/output (d 0 C d 15 ) direction control, and when active, drives data from the selected memory onto the data bus. we# must be driven to v ih (inactive) during a read access. 4.1.2 output disable with oe# at a logic-high level (v ih ), the device outputs are disabled. outputs (d 0 Cd 15 ) are placed in a high-impedance state. table 5. card signal values for the card's bus operations and modes bus operation/mode reset# cel# ceh# oe# we# a 1 bs8# d 8 C15 d 0C7 notes word read v ih v il v il v il v ih x x high low 1, 2, 4, v ih v ih v il v il v ih x x high low 1, 2, 4, 5 v ih v il v ih v il v ih x x high low 1, 2, 4, 5 word write v ih v il v il v ih v il x x high low 1, 2, 4 v ih v ih v il v ih v il x x high low 1, 2, 4, 6 v ih v il v ih v ih v il x x high low 1, 2, 4, 6 manufacturer id v ih v il v il v il v ih v il x 00h 89h device id v ih v il v il v il v ih v ih x 00h id 3 standby v ih xv ih x x x x high-z high-z v ih v ih x x x x x high-z high-z output disable v ih xxv ih v ih x x high-z high-z reset/power-down v il x x x x x x high-z high-z
e IFM004G/ifm008g/ifm016g 11 preliminary notes: 1. x can be v il or v ih for control signals and address. 2. busy# is v ol when the wsm is executing internal write or block erase algorithms. it is v oh when the wsm is not busy, in erase suspend mode, or deep power-down mode. 3. the device code can be 14h, or 15h. software should check for both cases for compatibility with future cards. 4. high indicates high byte data, low indicates low byte data. 5. both memory bytes will be read from memory as the cards memory component data bus is word-wide and does not provide for individual byte access. the bus operation is non-compliant with the pcmcia pc card standard as the pc card standard specifies a byte read operation instead of a word read operation for the listed signal conditions. 6. both memory bytes will be written to memory as the cards memory component data bus is word-wide and does not provide for individual byte access. the bus operation is non-compliant with the pcmcia pc card standard as the pc card standard specifies a byte write operation instead of a word write operation for the listed signal conditions. if a host system desires a byte write operation instead of a word write operation, then the host system must write v ih to the unwanted active byte (which should be inactive according the pc card standard ) in order to prevent the unwanted active byte from being written to card memory. 4.1.3 standby if both cel# and ceh# are at a logic-high level (v ih ), the card enters standby mode. standby operation disables much of the cards circuitry and substantially reduces device power consumption. the outputs (d 0 Cd 15 ) are placed in a high- impedance state independent of the status of oe#. if the host deselects the card during a write or erase, the card continues to function and consume normal active power until the operation completes. 4.1.4 reset/power-down reset# at v il initiates the reset/power-down mode. in read modes, reset#-low deselects the cards memory, places output drivers in a high-impedance state, and turns off numerous internal memory circuits. reset# must be held low for a minimum of t w . time t su is required after return from reset mode until initial memory access outputs are valid. after this wake-up interval, normal operation is restored. the cui is reset to read array mode and all memory device status registers are set to 80h. during block erase, write, or lock-bit configuration modes, reset#-low will abort the operation busy# transitions low and remains low for a maximum time of t w + t su until the reset operation is complete. memory contents being altered are no longer valid; the data may be partially corrupted after a write operation or partially altered after an erase or lock-bit configuration operation. time t su is required after reset# goes to logic-high (v ih ) before another command can be written. as with any automated device, it is important to assert reset# during system reset. w hen the system comes out of reset, it expects to r ead data from the flash memory. automated flash memories provide status information when accessed during block erase, write, or lock-bit configuration modes. if a cpu reset occurs with no flash memory reset, proper initialization may not occur because the flash memory may be providing status information instead of array data. intel ? flash memories allow proper initialization following a system reset thr ough the use of the reset# input. in this application, reset# is controlled by the same signal that resets the system cpu.
IFM004G/ifm008g/ifm016g e 12 preliminary reserved for future implementation reserved for future implementation (blocks 32 through 62) reserved for future implementation reserved for future implementation (blocks 2 through 30) reserved for future implementation reserved for future implementation block 63 block 31 block 1 block 0 lock configuration reserved for future implementation block 0 master lock configuration manufacturer code device code 3fffff 3f0003 3f0002 3f0000 3effff 1effff 1f0003 1f0002 1f0000 01ffff 010003 010002 010000 00ffff 000004 000003 000002 000001 000000 32 mbit 64 mbit word address a[22-1]: 64 mbit a[21-1]: 32 mbit block 31 lock configuration block 63 lock configuration block 1 lock configuration 0606_06 notes: 1. data is always given on the low byte (upper byte contains 00h). 2. memory shown is accessed by the read identifier codes command only and is physically distinct from the cards flash memory array. 3. master lock function of the cards underlying memory devices is not a card function. the master lock configuration information identified in the above memory map is shown only for the sake of consistency between the illustrated memory map and a corresponding memory map shown in the datasheet for the memory devices. figure 3. device identifier code memory map 4.1.5 read identifier codes the read identifier codes operation outputs the manufacturer code, device code, block lock configuration codes for each block, and the master lock configuration code (see figure 3) using the manufacturer and device codes, the system cpu can automatically match the device with its proper algorithms. the block lock and master lock configuration codes identify locked and unlocked blocks and master lock-bit setting. 4.1.6 write writing commands to the cui enables reading of device data, query, identifier codes, inspection and clearing of the status register, as well as block erasure, writing of data and lock-bit configuration. the block erase command requires appropriate command data and an address within the block to be erased. the word write command requires the command and address of the location to be written. the write to buffer command requires the command, starting address of the memory region to be written and the number of words to be written to the write buffer. set master and block lock-bit commands require the command and address within the device (master lock) or block within the device (block lock) to be locked. the clear block lock-bits command requires the command and address within the device. the cui does not occupy an addressable memory location. it is part of each memory device and is written when the device is enabled and we# is active. the address and data needed to execute a command are latched on the rising edge of we# or the first edge of cel# or ceh# that disables the device. write cycle timing is specified in section 9.2 ( write operations ). 4.2 decode logic the cards decode logic enables the appropriate memory component during a read or write access of card memory. unused upper addresses for the 5 volt series 200 miniature card will not be decoded. the address decoding will wrap around at the cards density.
e IFM004G/ifm008g/ifm016g 13 preliminary 5.0 command definition the operations of the cards memory device(s) are selected by the writing of specific commands into the cui. the 5 volt series 200 miniature card implements two command sets: the basic command set and the scaleable command set. the basic command set is backward compatible with the series 100 miniature card with the exception that write (program) suspend is not supported in the 5 volt series 200. the scaleable command set adds three capabilities to the miniature card in addition to the basic command set: 1. common flash interface (cfi) 2. buffered writes which employ a 32-byte write buffer to allow higher performance writes than available with the basic command set; and 3. a configurable busy# output. 5.1 basic command set table 6 presents the 5 volt series 200 miniature cards basic command set. the table indicates that the commands require one or more bus cycles to implement. the table and notes following the table describe each bus cycle. complete descriptions of the individual commands follow in subsections of the current document section. 5.1.1 read array command upon initial device power-up and after exit from reset/power-down mode, the cards memory devices default to read array mode. this operation is also initiated by writing the read array command to a memory device. the device remains enabled for reads until another command is written. once the internal wsm has started a block erase, write, or lock-bit configuration, the device will not recognize the read array command until the wsm completes its operation unless the wsm is suspended via an erase suspend command.
IFM004G/ifm008g/ifm016g e 14 preliminary table 6. basic command set definitions (9) command bus cycles req'd. notes first bus cycle second bus cycle oper (1) addr (2) data (3,4) oper (1) addr (2) data (3,4) read array 1 write x xxffh read identifier codes 3 2 5 write x xx90h read ia id read status register 2 write x xx70h read x srd clear status register 1 write x xx50h word write 2 6, 7 write x xx40h or xx10h write wa wd block erase 2 7 write x xx20h write ba xxd0h block erase suspend 1 7 write x xxb0h block erase resume 1 7 write x xxd0h set block lock-bit 2 write x xx60h write ba xx01h clear block lock-bits 2 8 write x xx60h write x xxd0h notes: 1. card signal values for the identified bus operations are defined in table 5. 2. x = any valid address within the device. ia = identifier code address: ba = address within the block being erased or locked. wa = address of memory location to be written. 3. srd = data read from status register. wd = data to be written at location wa. data is latched on the rising edge of we#. id = data read from identifier codes. 4. the upper byte of the data bus during command writes is a dont care (x). 5. following the read identifier codes command, read operations access manufacturer, device, block lock, and master lock codes. see read identifier section for read identifier code data. 6. either xx40h or xx10h are recognized by the wsm as the word-write command setup. 7. the issue of a block erase or write-word command to a locked block will fail. 8. the clear block lock-bits operation simultaneously clears all block lock-bits. 9. commands other than those shown above are reserved by intel for future device implementations and should not be used.
e IFM004G/ifm008g/ifm016g 15 preliminary 5.1.2 read identifier codes command the identifier code operation is initiated by writing the read identifier codes command to a memory device. following the command write, read cycles from addresses shown in figure 3 retrieve the manufacturer, device, block lock configuration and master lock configuration codes (see table 7 for identifier code values). to terminate the operation, write another valid command. the read identifier codes command is valid only when the wsm is off or the device is suspended. following the read identifier codes command, the following information can be read: table 7. identifier codes (1) code address (1) data manufacture code 00000 (00) 89 device code 32-mbit 00001 (00) 14 64-mbit 00001 (00) 15 block lock configuration x 0002 (2) block is unlocked dq 0 = 0 block is locked dq 0 = 1 reserved for future use dq 1 C7 master lock configuration (3) 00003 device is unlocked dq 0 = 0 device is locked dq 0 = 1 reserved for future use dq 1C7 notes: 1. data is always presented on the low byte (upper byte contains 00h). 2. x selects the specific blocks lock configuration code. see figure 3 for the device identifier code memory map. 3. see 5 volt intel ? strataflash? memory; 28f320j5 and 28f640j5 datasheet for a description of master lock configuration information. for 5 volt series 200 miniature cards the master lock configuration byte should indicate that the device is unlocked (dq 0 = 0). 5.1.3 read status register command the status register may be read to determine when a block erase, write, or lock-bit configuration operation is complete and whether the operation completed successfully. table 8 defines the content and format of the status register. the register may be read at any time by writing the read status register command. after writing this command, all subsequent read operations output data from the status register until another valid command is written. the status register contents are latched on the falling edge of oe# or the first edge of cel# and ceh# that enables the device (see table 5, card signal values for the cards bus operations and modes ). oe# must toggle to v ih or the device enter standby mode (table 5) before further reads to update the status register latch. during a word write, write to buffer, block erase, set lock-bit, or clear lock-bit command sequence, only sr.7 is valid until the write state machine completes or suspends the operation. device i/o pins dq 0 Cdq 6 and dq 8 Cdq 15 are placed in a high- impedance state. when the operation completes or suspends (check status register bit 7), all contents of the status register are valid when read. 5.1.4 clear status register command status register bits sr.5, sr.4, sr.3, and sr.1 are set to 1s by the wsm and can only be reset by the clear status register command. these bits indicate various failure conditions (see table 8). by allowing system software to reset these bits, several operations (such as cumulatively erasing or locking of multiple blocks or writing of several bytes in sequence) may be performed. the status register may be polled to determine if an error occurred during the sequence. to clear the status register, the clear status register command (50h) is written. the clear status register command is only valid when the wsm is off or the device is suspended.
IFM004G/ifm008g/ifm016g e 16 preliminary table 8. status register definitions (1) wsms ess eclbs pslbs vpens r dps r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 high z when busy? status register bits notes: no yes yes yes yes yes yes yes sr.7 = write state machine status 1 = ready 0 = busy sr.6 = erase suspend status 1 = block erase suspended 0 = block erase in progress/completed sr.5 = erase and clear lock-bits status 1 = error in block erasure or clear lock-bits 0 = successful block erase or clear lock-bits sr.4 = write and set lock-bit status 1 = error in write operation or set master/block lock-bit 0 = successful write operation or set master/block lock bit sr.3 = programming voltage status 1 = low programming voltage detected, write operation aborted 0 = programming voltage ok sr.2 = reserved for future enhancements sr.1 = device protect status 1 = master lock-bit, block lock-bit and/or reset# (rp#) lock detected, operation abort 0 = unlock sr.0 = reserved for future enhancements check busy# or sr.7 to determine block erase, write (program), or lock-bit configuration completion. sr.6 Csr.0 are not driven while sr.7 = 0. if both sr.5 and sr.4 are 1s after a block erase or lock-bit configuration attempt, an improper command sequence was entered. sr.3 does not provide a continuous memory device (write) programming voltage level indication. the wsm interrogates and indicates the programming voltage level only after block erase, word write, write to buffer, set block/master lock-bit, or clear block lock-bits command sequences. sr.1 does not provide a continuous indication of master and block lock-bit values. the wsm interrogates the master lock-bit, block lock-bit, and reset# (rp#) only after block erase, write word, write to buffer or lock-bit configuration command sequences. it informs the system, depending on the attempted operation, if the block lock-bit is set, master lock-bit is set, and/or reset# (rp#) is not v hh . read the block lock and master lock configuration codes using the read identifier codes command to determine master and block lock-bit status. sr.2 and sr.0 are reserved for future use and should be masked when polling the status register. note: 1. see the 5 volt intel ? strataflash? memory; 28f320j5 and 28f640j5 datasheet (order number 290606) for a description of the master lock-bit. for 5 volt series 200 miniature cards, the master lock-bit should always be = 0 and should not interfere with any of the cards write or erase operations. the bit is referenced in the table for consistency of definition between the card and card memory device datasheets as the card status register information is actually provided by whatever memory device receives the read status register command.
e IFM004G/ifm008g/ifm016g 17 preliminary table 9. extended status register definitions wbs reserved bit 7 bits 6 C0 high z when busy? status register bits notes: no yes xsr.7 = write buffer status 1 = write buffer available 0 = write buffer not available xsr.6 Cxsr.0 = reserved for future enhancements after a buffer-write command, xsr.7 = 1 indicates that a write buffer is available. sr.6Csr.0 are reserved for future use and should be masked when polling the status register. 5.1.5 block erase command erase is executed one block at a time and initiated by a two-cycle comm and. a block erase setup is first written, followed by an block erase confirm. this command sequence requires an appropriate address within the block to be erased (erase changes all block data to ffh). block preconditioning, erase, and verify are handled internally by the wsm (invisible to the system). after the two-cycle block erase s equence is written, the device automatically outputs status register data when read. the cpu can detect block erase completion by analyzing the logic level of the sts pin or status register bit sr.7. toggle oe#, cel# or ceh# to update the status register. when the block erase is complete, status register bit sr.5 should be checked. if a block erase error is detected, the status register should be cleared before system software attempts corrective actions. the cui remains in read status register mode until a new command is issued. this two-step command sequence of set-up followed by execution ensures that block contents are not accidentally erased. an invalid block erase command sequence will result in both status register bits sr.4 and sr.5 being set to 1. successful block erase requires that the corresponding block lock-bit be cleared. if block erase is attempted when the corresponding block lock-bit is set, sr.1 and sr.5 will be set to 1. 5.1.6 block erase suspend command the block erase suspend command allows block- erase interruption to read or write data in another block of memory. once the block erase process starts, writing the block erase suspend command requests that the wsm suspend the block erase sequence at a predetermined point in the algorithm. the device outputs status register data when read after the block erase suspend command is written. polling status register bit sr.7 then sr.6 can determine when the block erase operation has been suspended (both will be set to 1). the busy# output will also transition to v oh . specification t whrh defines the block erase suspend latency. at this point, a read array command can be written in order to read data from blo cks other t han that which is suspended. a word-write or write-to-buffer command sequence can also be issued during erase suspend to write data in other blo cks. during a write operation with block erase suspended, status register bit sr.7 will return to 0 and the busy# output will transition to v ol . the only other valid commands while block erase is suspended are read query, read status register, clear status register, configure, and block erase resume. after a block erase resume command is written to the flash memory, the wsm will continue the block erase process. status register bits sr.6 and sr.7 will automatically clear and the busy# output will return to v ol . after the erase resume command is written, the device automatically outputs status register data when read. block erase cannot resume until write operations initiated during block erase suspend have completed.
IFM004G/ifm008g/ifm016g e 18 preliminary 5.1.7 word-write command word-write commands are executed in a two- cycle command sequence. word-write command setup (standard 40h or alternate 10h) is written in the first cycle and then followed in the next cycle by a second write that specifies the address and data (latched on the rising edge of we#) to be written in memory. the wsm then takes over, controlling the word-write and word-write verify algorithms internally. after the word-write command sequence is written, the device automatically outputs status register data when read. the cpu can detect the completion of the write event by analyzing the logic state of the busy# output or status register bit sr.7. when the word-write operation is complete, status register bit sr.4 should be checked. if a write error is detected, the status register should be cleared. the internal wsm verify only detects errors for 1s that do not successfully program to 0s. the cui remains in read status register mode until it receives another command. successful write operations require that the corresponding block lock-bit be cleared. if a word write operation is attempted when the corresponding block lock-bit is set, sr.1 and sr.4 will be set to 1. 5.1.8 set block lock-bit command a flexible block locking and unlocking scheme is enabled via a combination of block lock-bits. the block lock-bits gate memory write and erase operations. individual block lock-bits can be set using the set block lock-bit command. set block lock-bit commands are invalid while the wsm is running or the device is suspended. set block lock-bit commands are executed by a two-cycle s equence. the set block lock-bit setup along with appropriate block or device address is written followed by either the set block lock-bit confirm (and an address within the block to be locked). the wsm then controls the set lock-bit algorithm. after the sequence is written, the device automatically outputs status register data when read. the cpu can detect the completion of the set lock-bit event by analyzing the logic state of the busy# pin output or status register bit sr.7. when the set lock-bit operation is complete, status register bit sr.4 should be checked. if an error is detected, the status register should be cleared. the cui will remain in read status register mode until a new command is issued. this two-step sequence of set-up followed by execution ensures that lock-bits are not accidentally set. an invalid set block lock-bit command will result in status register bits sr.4 and sr.5 being set to 1. 5.1.9 clear block lock-bits command all set block lock-bits are cleared in parallel via the clear block lock-bits command. this command is invalid while the wsm is running or the device is suspended. clear block lock-bits command is executed by a two-cycle s equence. a clear block lock-bits setup is first written followed by the clear block lock-bits confirm. the device automatically outputs status register data when read. the cpu can detect completion of the clear block lock-bits event by analyzing the logic state of the busy# pin output or status register bit sr.7. when the operation is complete, status register bit sr.5 should be checked. if a clear block lock-bit error is detected, the status register should be cleared. the cui will remain in read status register mode until another command is issued. this two-step sequence of set-up followed by execution ensures that block lock-bits are not accidentally cleared. an invalid clear block lock- bits command sequence will result in status register bits sr.4 and sr.5 being set to 1. if a clear block lock-bits operation is aborted due to v cc transitioning out of valid range or reset# active transition, block lock-bit values are left in an undetermined state. a repeat of the clear block lock-bits command is then required to initialize block lock-bit contents to known values. 5.2 scaleable command set table 10 presents the 5 volt series 200 miniature cards scaleable command set. the table indicates that the commands require one or more bus cycles to implement. the table and notes following the table describe each bus cycle. complete descriptions of the individual commands follow in subsections of the current document section.
e IFM004G/ifm008g/ifm016g 19 preliminary table 10. scaleable command set definitions (10) command bus cycles req'd. notes first bus cycle second bus cycle oper (1) addr (2) data (3,4) oper (1) addr (2) data (3,4) read query 3 2 write x xx98h read qa qd write to buffer > 2 5, 6, 7, 8, 9 write ba xxe8h write ba n ? confirm 1 6, 7 write x xxd0h configuration 9 notes: 1. card signal values for the identified bus operations are defined in table 5, signal values for the cards bus operations and modes . 2. x = any valid address within the device. qa = query database address. ba = block address. 3. qd = data read from query database. cc = configuration code. 4. the upper byte of the data bus during command writes is a dont care. 5. after the first bus cycle of the write to buffer command, check the extended status register to make sure the write buffer i s available for writing. if the buffer is available for writing, proceed with the second bus cycle; otherwise, continue repeating the first bus cycle and checking the extended status register in turn until the buffer becomes available; when the buffer becomes available, proceed with the second bus cycle of the write to buffer command. 6. the number of words to be written to the write buffer = n + 1, where n = word count argument. the word count range on this device is n = 0000h to n = 000fh. writing a word count outside the buffer boundary causes unexpected results and should be avoided. the third and consecutive bus cycles of a write to buffer command sequence, as determined by n, are for writing data into the write buffer. in the third bus cycle a device start address is given along with the write buffer data. subsequent write cycles provide additional device addresses and data. all subsequent addresses must lie within the start address plus the count. the confirm command (xxd0h) is expected after exactly n + 1 write cycles; any other command at that point in the sequence aborts the write to buffer operation. please see the 5 volt intel ? strataflash? memory; 28f320j5 and 28f640j5 datasheet for additional information on the write to buffer command. 7. the write buffer operation does not begin until a confirm command is issued. 8. the issue of a write to buffer command to a locked block will fail. 9. the configuration command is not supported on the 5 volt series 200 miniature card. the configuration command serves to program the configurable status output (sts output pin) of a memory device. to satisfy the miniature card implementers forum specification the sts output pin for all card memory devices must be configured as a ry/by# pin to generate the cards busy# output signal. at card power-up the sts output for all devices defaults to ry/by# pin operation; thereafter, host software shall not issue the configuration command. 10. commands other than those shown above are reserved for future use and should not be used.
IFM004G/ifm008g/ifm016g e 20 preliminary 5.2.1 block write command to write to the flash device write buffer, a write to buffer command sequence is initiated. a variable number of bytes, up to the buffer size, can be loaded into the buffer and written to the flash device. first, the write to buffer setup command is issued along with the block address of the memory device erase block to which the buffer content will be written. at this point, the extended status register information (reference table 9) is loaded into the register and xsr.7 reverts to reflecting "buffer available" status. whenever the memory device is read immediately after receiving a write to buffer command, the extended status register content will be presented by the memory. if xsr.7=0, the write buffer is not available for writing. when xsr.7 = 1, the memory device will allow data to be written to the write buffer. to determine when the write buffer can be written, continue to monitor xsr.7 until xsr.7=1 by repeating the sequence of first issuing the write to buffer setup command along with the appropriate block address, and then reading the extended status register. when the write buffer becomes available for writing, a word count (n) is given to the memory device with the block address of the memory device erase block to which the buffer content will be written. on the next write, a device start address is given along with the write buffer data. for maximum programming performance and lower power, align the start address at the beginning of a write buffer boundary. subsequent writes provide additional device addresses and data. all subsequent addresses must lie within the start address plus the count. after the final buffer data is given, a write confirm command is issued. this initiates the wsm (write state machine) to begin copying the buffer data to the flash memory. if a command other than write confirm is written to the device, an invalid command/sequence error will be generated and status register bits sr.5 and sr.4 will be set to a 1. for additional buffer writes, issue another write to buffer setup command and check xsr.7. the write buffers can be loaded while the wsm is busy as long as xsr.7 indicates that a buffer is available. if an error occurs while a device is writing data to memory, the device will stop writing, and status register bit sr.4 will be set to a 1 to indicate a write operation failure. any time a media failure occurs during a write or an erase (for which sr.4 or sr.5 is set, respectively), the device will not except any more buffered write commands. additionally, if the user attempts to write past an erase block boundary with a write to buffer command, the device will abort the write. this will generate an invalid command/sequence error (botch) and status register bits sr.5 and sr.4 will be set to a 1. to clear sr.4 and/or sr.5 issue a clear status register command. successful writing to an erase block requires that the blocks associated block lock-bit bit be reset. if the block lock-bit is set, the erase block is locked. a write to buffer command which attempts to write data to the locked block will fail and result in sr.1 and sr.4 being set to 1. 5.2.2 configuration command the configuration command is not supported on the 5 volt series 200 miniature card. the configuration command serves to program the configurable status output (sts output pin) of a memory device. to satisfy the pcmcia miniature card specification the sts output pin for all card memory devices must be configured as a ry/by# pin to generate the cards busy# output signal. at card power-up the sts output for all devices defaults to ry/by# pin operation; thereafter, host software shall not issue the configuration command. 5.2.3 read query command the scs (scaleable command set) read query command causes the flash component to output the common flash interface (cfi) query structure or database information. the common flash interface provides a standard means for a flash memory to tell a host system about the memory's architecture, algorithms and characteristics. see ap-646 common flash interface (cfi) and command sets (order number 292204) for a full description of cfi. writing the read query command to the memory puts it in read query mode. while in read query mode, the memory responds to read bus operations with data from a rom instead of data from the flash array data. the data in the rom describes the memory component to which the ready query command is addressed.
e IFM004G/ifm008g/ifm016g 21 preliminary as the definition of cfi data presented by a card memory device is quite extensive, the definition is not repeated as part of the current document. refer to the 5 volt intel ? strataflash? memory; 28f320j5 and 28f640j5 datasheet for a complete definition of the card memorys cfi data and the read query command by which the data is accessed. 6.0 card attribute information the card attribute information consists of a miniature card attribute information structure (ais) in accordance with the miniature card implementers forum as well as a card information structure (cis) in compliance with the pcmcia pc card specification. these two structures co-exist for compatibility with both industry standards. this allows the 5 volt series 200 miniature card to function in both pc card and miniature card environments. the card attribute information data for the 5 volt series 200 miniature card is found in section 6.3. for more information on the description of these structures refer to the appropriate specification. caution: the card attribute information data is located in block 0. this information is not write protected and should not be erased by the system software if this information is needed for card recognition. 6.1 card information structure the cis begins at address 0000h (device tuple) of the cards memory. the cis data resides only in the low byte of the word. it contains a variable length chain of data blocks (tuples) that conform to a basic format. see table 11 for the cis memory map. 6.2 attribute information structure the ais begins at address 0010h (identifier byte) of the cards memory. the ais data resides only in the low byte of the word. it contains a fixed list of data information that ends at address 00ffh. see table 12 for the ais memory map. note: all addresses listed in table 11 and table 12 are word addresses. table 11. cis memory map tuple name description tuple code address location cistpl_device device information 01h 0h - 04h cistpl_null null (ignore) 00h 05h - 0dh cistpl_mini miniature card ais (vendor unique) 80h 0eh - ffh cistpl_devicegeo device geometry information 1eh 100h - 107h cistpl_manfid manufacturer identification string 20h 108h - 10dh cistpl_funcid function class identification 21h 10eh - 111h cistpl_longlink_c longlink to common memory 12h 112h - 117h cistpl_vers_1 level 1 version/product information 15h 118h - 167h cistpl_jedec_c jedec id 18h 168h - 16bh cistpl_end the end-of-chain tuple ffh 16ch - 16dh
IFM004G/ifm008g/ifm016g e 22 preliminary table 12. ais memory map ais section description address location identification data identifies card type 10h - 3fh compatibility data describes attributes of card 40h - 4fh not used reserved for future use 50h - ffh 6.3 cis data cis data is located in memory and describes the 5 volt series 200 miniature card as follows: address values description 00h 01h cistpl_device 01h 03h tpl_link 02h 53h flash = 150 ns 52h flash = 200 ns 03h 0eh card size: 4 mb 1eh card size: 8 mb 3eh card size: 16 mb 04h ffh end of device 05h - 0dh 00h cistpl_null 0eh 80h cistpl_min 0fh f0h tpl_link 10h 99h identifier 11h 10h rev 1.0 compliant 12h 65h 4-mb,150 ns ais checksum 5bh 8-mb, 200 ns ais checksum 52h 16-mb, 200 ns ais checksum 13h 49h manufacturer name i 14h 4eh n 15h 54h t 16h 45h e address values description 17h 4ch l 18h 20h space 19h 43h c 1ah 4fh o 1bh 52h r 1ch 50h p 1dh 4fh o 1eh 52h r 1fh 41h a 20h 54h t 21h 49h i 22h 4fh o 23h 4eh n 24h - 26h 00h null 27h 53h card name s 28h 45h e 29h 52h r 2ah 49h i 2bh 45h e 2ch 53h s 2dh 20h space 2eh 32h 2
e IFM004G/ifm008g/ifm016g 23 preliminary address values description 2fh 30h 0 30h 30h 0 31h 20h space 32h 43h c 33h 41h a 34h 52h r 35h 44h d 36h - 3ah 00h null 3bh 01h 1 technology device 3ch - 3fh 00h reserved space set to 00h 40h 00h flash 41h 89h device jedec manufacturer id 42h 14h 4-mb device component jedec id 15h 8-mb device component jedec id 15h 16-mb device component jedec id 43h 03h 4 mb 07h 8 mb 0fh 16 mb 44h 00h no x.x v accesses 45h 00h no 3.3 v access time 46h 0fh 150 ns 5.0 v access time 14h 200 ns 5.0 v access time 47h 00h no x.x v accesses 48h 00h no 3.3 v accesses 49h 47h 40 ma read/70 ma write @ 5.0 v address values description 4ah 01h 100 m a standby - 4 mb 01h 180 m a standby - 8 mb 02h 340 m a standby - 16 mb 4bh - 4fh 00h reserved 50h - ffh 00h null / not used 100h 1eh cistpl_devicegeo 101h 06h tpl_link 102h 02h dgtpl_bus 103h 11h dgtpl_ebs 104h 01h dgtpl_rbs 105h 01h dgtpl_wbs 106h 01h dgtpl_part = 1 107h 01h flash device interleave 108h 20h cistpl_manfid 109h 04h tpl_link 10ah 89h tplmid_manf: lsb (intel jedec id) 10bh 00h tplmid_manf: msb 10ch 12h 4 mb - 150 ns 21h 8 mb - 200 ns 31h 16 mb - 200 ns 10dh 86h tplmid_card msb value series 200 card 10eh 21h cistpl_funcid 10fh 02h tpl_link 110h 01h tplfid_function : memory 111h 00h tplfid_sysinit 112h 12h cistpl_longlink_c 113h 04h tpl_link
IFM004G/ifm008g/ifm016g e 24 preliminary address values description 114h 00h lowest byte 115h 00h mid byte 116h 02h mid byte 117h 00h highest byte 118h 15h cistpl_vers1 119h 4eh tpl_link 11ah 05h tpllv1_major 11bh 00h tpllv1_minor 11ch 49h tpllv1_info i 11dh 6eh n 11eh 74h t 11fh 65h e 120h 6ch l 121h 00h end text 122h 53h s 123h 45h e 124h 52h r 125h 49h i 126h 45h e 127h 53h s 128h 20h space 129h 32h 2 12ah 30h 0 12bh 30h 0 12ch 20h space 12dh 46h f 12eh 4ch l 12fh 41h a 130h 53h s 131h 48h h address values description 132h 20h space 133h 4dh m 134h 49h i 135h 4eh n 136h 49h i 137h 41h a 138h 54h t 139h 55h u 13ah 52h r 13bh 45h e 13ch 20h space 13dh 43h c 13eh 41h a 13fh 52h r 140h 44h d 141h 00h end text 142h 30h 4 mb 30h 8 mb 31h 16 mb 143h 34h 4 mb 38h 8 mb 36h 16 mb 144h 20h space 145h 00h end text 146h 43h c 147h 4fh o 148h 50h p 149h 59h y 14ah 52h r 14bh 49h i 14ch 47h g
e IFM004G/ifm008g/ifm016g 25 preliminary address values description 14dh 48h h 14eh 54h t 14fh 20h space 150h 49h i 151h 4eh n 152h 54h t 153h 45h e 154h 4ch l 155h 20h space 156h 43h c 157h 4fh o 158h 52h r 159h 50h p 15ah 4fh o 15bh 52h r 15ch 41h a 15dh 54h t 15eh 49h i 15fh 4fh o 160h 4eh n 161h 20h space address values description 162h 31h 1 163h 39h 9 164h 39h 9 165h 37h 7 166h 00h end text 167h ffh end of list 168h 18h cistpl_jedec_c 169h 02h tpl_link 16ah 89h manufacturer id 16bh 14h 4 mb card device component jedec id 15h 8 mb card device component jedec id 15h 16 mb card device component jedec id 16ch ffh cistpl_end 16dh 00h invalid address
IFM004G/ifm008g/ifm016g e 26 preliminary 7.0 electrical specifications 7.1 absolute maximum ratings* commercial operating temperature during read, block erase, write, and lock-bit configuration . C20 c to +70 c (1) temperature under bias ........ C10 c to +80 c storage temperature................. C65 c to +125 c voltage on any pin .................... C2.0 v to +7.0 v (2) output short circuit current.....................100 ma (3) notice: this datasheet contains preliminary information on new products in production. do not finalize a design with this information. revised information will be published when the product is available. verify with your local intel sales office that you have the latest datasheet before finalizing a design. * warning: stressing the device beyond the "absolute maximum ratings" may cause permanent damage. these are stress ratings only. operation beyond the "operating conditions" is not recommended and extended exposure beyond the "operating conditions" may effect device reliability. notes: 1. operating temperature is for commercial product defined by this specification. 2. all specified voltages are with respect to gnd. minimum dc voltage is C0.5 v on input/output pins and C0.2 v on v cc pin. during transitions, this level may undershoot to C2.0 v for periods <20 ns. maximum dc voltage on input/output pins and v cc is v cc +0.5 v which, during transitions, may overshoot to v cc +2.0 v for periods <20 ns. 3. output shorted for no more than one second. no more than one output shorted at a time. 7.2 operating conditions temperature and v cc operating conditions symbol parameter notes min max unit test condition t a operating temperature C20 +70 c ambient temperature v cc v cc supply voltage (5 v 5%) 4.75 5.25 v 7.3 capacitance (1) t a = +25 c, f = 1 mhz symbol parameter typ max unit condition c in input capacitance 6 8 pf v in = 0.0 v c out output capacitance 8 12 pf v out = 0.0 v note: 1. sampled, not 100% tested.
e IFM004G/ifm008g/ifm016g 27 preliminary 7.4 dc characteristics test sym parameter notes typ max unit conditions i li input load current 1,4 20 m a v cc = v cc max, v in = v cc or gnd i lo output leakage current 1 20 m a v cc = v cc max, v in = v cc or gnd i ccs v cc standby current m a v cc = v cc max 4-mbyte card 1,3 100 170 cel# = ceh# = reset# =v cc 0.2 v 8-mbyte card 1,3 180 320 16-mbyte card 1,3 340 620 i ccd v cc deep power-down current m a reset#, gnd 0.2v i out (reset) = 0 ma 4-mbyte card 1,3 100 145 8-mbyte card 1,3 180 270 16-mbyte card 1,3 340 520 i ccr v cc read current 1 35 55 ma v cc = v cc max, cel#/ceh# = gnd, f = 5 mhz, i out = 0 ma i ccw v cc word write or set lock-bit current 1,3 35 60 ma cmos inputs i cce v cc block erase or clear lock-bits current 1,3 35 70 ma cmos inputs i cces v cc block erase suspend current 1,2 10 ma cel# = ceh# = v ih notes: 1. all currents are in rms unless otherwise noted. these currents are valid for all product versions (speeds). contact intels application support hotline or your local sales office for information about typical specifications. 2. i cces is specified with the cards memory de-selected. if read or word write occurs while in erase suspend mode, the cards current draw is the sum of i cces and either i ccr (read) or i ccw (write). 3. cmos inputs are either v cc 0.2 v or gnd 0.2 v. 4. exceptions: with v in = gnd, the leakage current on cel#, ceh# will be < 50 m a each due to internal pull-up resistors.
IFM004G/ifm008g/ifm016g e 28 preliminary 7.4 dc characteristics (continued) test sym parameter notes min max unit conditions v il input low voltage C0.5 0.8 v v ih input high voltage 0.7 v cc v cc + 0.5 v v ol output low voltage 0.1 v cc vv cc = v cc min i ol = 4.0 ma v oh output high voltage 0.9 v cc v v cc = v cc min i oh = C1 ma v lko v cc lockout voltage 0.7 v cc v test points input output 1.5 3.0 0.0 1.5 0620_04 note: 1. ac test inputs are driven at 3.0 v for a logic 1 and 0.0 v for a logic 0. input timing begins, and output timing ends, at 1.5 v. input rise and fall times (10% to 90%) < 10 ns. figure 4. transient input/output reference waveform for v cc = 5 v 5% (standard testing configuration) device under test 1.3v 1n914 c l out r = 3.3 k l w c includes jig capacitance l 0620_05 note: c l includes jig capacitance figure 5. transient equivalent testing load circuit test configuration capacitance loading value test configuration c l (pf) v cc = 5.0 v 5% 100
e IFM004G/ifm008g/ifm016g 29 preliminary 7.5 ac characteristics ac timing diagrams and characteristics are designed to meet or exceed the miniature card specification. 7.5.1 read operations ieee 4-, 8-, 16-mb cards symbol parameter min max unit t avav read cycle time 150 ns t avqv address access time 150 ns t elqv ce# access time 150 ns t glqv oe# access time 75 ns t ghqz output disable time from oe# inactive 75 ns t glqnz output enable time from oe# active (1) 5ns t elqnz output enable time from ce# active (1) 5ns t axqx data hold from address, ce#, or oe# change (whichever occurs first) 0ns t elgl ce# setup time to oe# active 0 ns t avgl address setup time to oe# active 20 ns t phqv busy# high to output delay 180 ns note: 1. sampled, not 100% tested.
IFM004G/ifm008g/ifm016g e 30 preliminary t t t t t t t t t t t t note 1 note 1 data valid a[25:0] cel#/ceh# oe# d[15:0] avav avqv avgl elgl elqnz elqv glqv glqnz ghqz ghqx ehqx axqx t phqv busy# 0620_06 note: 1. the filled area may be either high or low. figure 6. ac waveforms for read operations
e IFM004G/ifm008g/ifm016g 31 preliminary 7.5.2 write operations ieee 4-, 8-,16-mb cards symbol parameter min max unit t avav write cycle time 150 ns t wlwh we# pulse width 80 ns t avwl address setup time to we# active 20 ns t dvwh data setup time to we# inactive 50 ns t whdx data hold time from we# inactive 20 ns t whax address hold time from we# inactive 10 ns t wheh ce# hold time from we# inactive 10 ns t elwl ce# setup time to we# active (1) 0ns t ehwl ce# inactive time to we# active (1) 35 ns t whwl we# inactive time to we# active 30 ns t whrl we# (ce#) inactive time to busy# active 90 ns note: 1. these timings apply only if both ce#s (cel# and ceh#) are deasserted prior to we# asserted. t t t t t t t note 1 note 1 a[25:0] cel#/ceh# we# d[15:0] avav avwl whax wheh dvwh wlwh whdx 0620_07 figure 7. ac waveforms for write operations
IFM004G/ifm008g/ifm016g e 32 preliminary 7.5.3 power-up timing symbol parameter notes min max units t su (cel#/ceh#) ce# setup time 1 ms t su (reset#) reset# setup time 1 ms t pr v cc rising time 1 0.1 100 ms t w (reset#) reset# width 2 36 s notes: 1. the t pr is defined as a linear waveform in the period of 10% to 90%. even if the waveform is not a linear waveform, its rising time must meet this specification. 2. if reset# is asserted while a block erase, write, or lock-bit configuration operation is not executing, then the minimum required reset# pulse low time is 1 s. 3. a reset time, t phqv (reference section 8.4.1), is required from busy# or reset# going high until outputs are valid. v 2v cel#/ceh# hi-z t (cel#/ceh#) t (reset#) t t (reset#) reset# v @ 10% v cc v @ 90% cc ih cc su su w t (reset#) su t (reset#) w pr 0620_08 figure 8. power-up timing for systems supporting reset#
e IFM004G/ifm008g/ifm016g 33 preliminary 7.6 block erase, write, and lock-bit configuration performance (3,4) sym parameter notes min typ (1) max unit t whqv1 t ehqv1 write buffer word write time 2,5,6 tbd 12 tbd s t whqv2 t ehqv2 word write time (using word write command) 2,6 tbd 180 tbd s ? block write time (using write to buffer command) 2,6 tbd 1.6 tbd sec t whqv4 t ehqv4 block erase time 2 tbd 0.7 tbd sec t whqv5 t ehqv5 set lock-bit time 2 tbd 32 tbd s t whqv6 t ehqv6 clear block lock-bits time 2 tbd 0.3 tbd sec t whrh t ehrh erase suspend latency time to read 25 tbd s notes: 1. typical values measured at t a = +25 c and nominal voltages. assumes corresponding lock-bits are not set. subject to change based on device characterization. 2. excludes system-level overhead. 3. these performance numbers are valid for all speed versions. 4. sampled but not 100% tested. 5. these values are valid when the buffer is full, and the start address is aligned on a 32-byte boundary. 6. the maximum write time is the absolute maximum time it takes the write algorithm to complete. the overwhelming majority of the bits are written within the typical value specified. to maximize system performance, the busy# signal should be polled to determine the completion of a write operation.
IFM004G/ifm008g/ifm016g e 34 preliminary 8.0 packaging figure 9 shows the outside dimensions of the 5 volt series 200 miniature card. for complete mechanical drawings refer to the miniature card specification. 3.5 mm 33 mm 38 mm 3.3v / 5v key x alignment notch latching notches y alignment notches 0620_09 figure 9. miniature card dimensions
e IFM004G/ifm008g/ifm016g 35 preliminary 9.0 ordering information IFM004G, shxxxxx where: i = intel fm = flash miniature card 004 = density in megabytes (004, 008, 016 available) g = revision shxxxxx = customer identifier 10.0 additional information order number document 210830 flash memory databook 297899 5 volt series 200 flash memory miniature card specification update 290606 5 volt intel ? strataflash? memory; 28f320j5 and 28f640j5 datasheet 297848 5 volt intel ? strataflash? memory; 28f320j5 and 28f640j5 specification update 292205 ap-647 5 volt intel ? strataflash? memory design guide 292204 ap-646 common flash interface (cfi) and command sets 292203 ap-644 migration guide to intel ? strataflash? memory note 3 ap-374 flash memory write protection techniques note: 1. please call the intel literature center at (800) 548-4725 to request intel documentation. inte rnational customers should contact their local intel or distribution sales office. 2. visit intels world wide web home page at http://www.intel.com for technical documentation and tools. 3. these documents can be located at the intel world wide web support site, http://www.intel.com/support/flash/memory

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